P4 Workshop

Programmable logic (FPGA) offers an appropriate technology for implementing switches with protocol independence and reconfigurability in the field, operating at high line rates. However, tooling is required to bridge the gap between the raw programmable hardware technology and the description of required packet processing functionality. In this talk, I will overview the XilinxSDNet methodology, which compiles a description in the PX language to an efficient FPGA implementation. PX and P4 have a great deal in common, being at the same level of abstraction and covering the same domain of interest. I will describe how we are now targeting P4 as the description language. The initial prototype involves a transformation from P4 to PX, and thenSDNet as a backend. The ultimate goal is to harness the emergent PIF intermediate representation, using a future open source P4 front end and a Xilinx-specific back end based on a refactoring of SDNet.